TY - GEN
T1 - Turn-off Analysis and Modeling of Releasing Loss in Snubber Capacitor Self-Balancing Circuits for Series-Connected SiC MOSFETs Applied to High-Voltage Pulsed Power Systems
AU - Niu, Jiaxuan
AU - Cheng, Xu
AU - Yang, Xu
AU - Chen, Yong
AU - Zhang, Fan
AU - Zhao, Kexin
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - SiC MOSFETs demonstrate superior characteristics such as high switching speed and high breakdown voltage, the development of series-connected SiC MOSFETs-based pulse power switches has emerged as a primary research truth. To meet the dynamic voltage balancing demands of series-connected SiC MOSFETs under ultra-fast switching conditions, the snubber capacitor self-balancing circuit provides advantages including simplicity, high reliability, and full-speed switching capability. However, the absence of quantitative analysis on releasing loss in this topology limits circuit design and optimization. Meanwhile, the modeling of the series-connected SiC MOSFETs turn-off process under ohmic loads is understudied, which increases the difficulty of loss modeling. This paper investigates the working principles and turn-off process of the topology, simplifies the model under ohmic load conditions, and proposes a method for analyzing the drain-source voltage rise rate of series-connected SiC MOSFETs under different delay combinations while establishing a releaseing loss model. Moreover, this method is scalable for extending the number of series-connected devices. The trends demonstrated by the model is verified by comparison of multiple simulation results.
AB - SiC MOSFETs demonstrate superior characteristics such as high switching speed and high breakdown voltage, the development of series-connected SiC MOSFETs-based pulse power switches has emerged as a primary research truth. To meet the dynamic voltage balancing demands of series-connected SiC MOSFETs under ultra-fast switching conditions, the snubber capacitor self-balancing circuit provides advantages including simplicity, high reliability, and full-speed switching capability. However, the absence of quantitative analysis on releasing loss in this topology limits circuit design and optimization. Meanwhile, the modeling of the series-connected SiC MOSFETs turn-off process under ohmic loads is understudied, which increases the difficulty of loss modeling. This paper investigates the working principles and turn-off process of the topology, simplifies the model under ohmic load conditions, and proposes a method for analyzing the drain-source voltage rise rate of series-connected SiC MOSFETs under different delay combinations while establishing a releaseing loss model. Moreover, this method is scalable for extending the number of series-connected devices. The trends demonstrated by the model is verified by comparison of multiple simulation results.
KW - SiC MOSFET
KW - series-connection
KW - voltage balanceing
UR - https://www.scopus.com/pages/publications/105019964358
U2 - 10.1109/WiPDA-Asia63772.2025.11183910
DO - 10.1109/WiPDA-Asia63772.2025.11183910
M3 - 会议稿件
AN - SCOPUS:105019964358
T3 - 2025 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia, WiPDA Asia 2025
BT - 2025 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia, WiPDA Asia 2025
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2025 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia, WiPDA Asia 2025
Y2 - 15 August 2025 through 17 August 2025
ER -