Theoretical total harmonic distortion evaluation based on digital to analogue converter mismatch to improve the linearity of successive approximation register analogue to digital converter

Mismatch in the binary-weighted capacitive digital-to-analog converter (DAC) greatly affects the linearity of the successive-approximation-register (SAR) ADC by deteriorating the total harmonic distortion (THD). In this study, a theoretical relationship between the THD and the mismatch error of DAC array in SAR ADC is derived through discrete Fourier transform (DFT) analysis of the time-based integral error (TIE) of the ADC's output codes, which has no specific requirement on the type of the input signals. Guided by the theoretical THD expression, the trade-off among the linearity, design complexity, power consumption and chip area can be balanced easily. The presented formula is verified by a design example of 12-bit SAR ADC with dynamic-element-matching (DEM) technique, where the 3-bit LSBs from the SAR ADC are used to generate the randomised DEM state according to the previous THD evaluation. The linearity is enhanced by 9 dB approximately with very low hardware complexity and extremely small extra power consumption of 2 μW.