Study on Influencing Factors of Voltage Unbalance Ratio in Snubber Capacitor Self-Balancing Circuits for Series-Connected Sic MOSFETs Applied to High-Voltage Pulsed Power Systems

SiC MOSFETS, with advantages such as high switching speed and high breakdown voltage, are a key focus in the development of pulsed power switches. The snubber capacitor self-balancing circuit, characterized by simplicity, high reliability, and full-speed switching capability, provides an effective solution for dynamic voltage balancing in seriesconnected SiC MOSFETS under extremely fast switching conditions. To meet the voltage withstand requirements of pulsed power switches, ranging from tens to hundreds kV, dozens of low-voltage SiC MOSFETS must be connected in series. However, factors such as loop impedance, gate drive delay, the count of switches connected in series, and duty cycle affect the voltage balancing capability of the topology, thereby influencing the voltage withstand limit and safe operation of each switch. This paper analyzes the working principle and waveforms of the snubber circuits, investigates the impact of influencing factors on voltage unbalance ratio and validates through LTspice simulations, and proposes solutions for further optimizing the voltage withstand and balancing capabilities of the topology.