Research on the Optimization Scheme of Arc Fault Detection Hardware Parameters Based on Bayesian Optimization

In DC system, continuous series arc fault may cause fire accident. However, complex algorithm model consumes a lot of hardware resources which is difficult to be applied in practice. It is necessary to optimize network parameters to improve operational efficiency. In this paper, arc fault experiment platform is built to acquire the arc fault current. Fault signal is decomposed based on Rbio3.1 wavelet to obtain arc fault features. The preliminarily built detection algorithm based on machine learning takes too long to meet the detection requirements of UL1699B standard. Taking the detection accuracy and detection speed as the optimization objectives, the optimization of parameters using Bayesian optimization method is discussed. By selecting the appropriate probabilistic surrogate model and acquisition function, the search efficiency is improved by Bayesian optimization with the help of historical information, and the best combination of hyper-parameters is determined. The optimized network prediction accuracy is improved and the hardware calculation burden is reduced. This optimization method is verified to help different network models achieve better hardware performance on STM32 and Raspberry Pi platform.