Printing Semiconductor–Insulator Polymer Bilayers for High-Performance Coplanar Field-Effect Transistors

Source–semiconductor–drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next-generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross-talk among different devices, and simplify the fabrication process of circuits. Here, a one-step, drop-casting-like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3-hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO₂ dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor–insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor–insulator bilayer structure is an ideal system for injecting charges into the insulator via gate-stress, and the thus-formed PS electret layer acts as a “nonuniform floating gate” to tune the threshold voltage and effective mobility of the transistors. Effective field-effect mobility higher than 1 cm² V⁻¹ s⁻¹ with an on/off ratio > 10⁷ is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits.