P-TICER: An Effective Parallel TICER Acceleration Method for Model Order Reduction

In the field of post simulation verification in in-tegrated circuit design, Time-Constant Equilibration Reduction (TICER) is a well-known and widely used algorithm for model order reduction. However, the TICER for large-scale circuits is time-consuming. Moreover, there is a contradiction between the node compression ratio and circuit sparsity. In this paper, an effective TICER-based optimization parellel acceleration algorithm called P-TICER is proposed. An adaptive circuit judgment partitioning strategy based on graph partitioning is proposed to partition circuits and perform multi-threaded parallel acceleration. The compression ratio and sparsity of the circuit are optimized and balanced. Moreover, RC-In-RC-Out structure is designed, which is realizable and seamlessly integra table with other simulators as it takes circuit netlists as input and output. We apply P- TICER to the RC circuits with two different types and nodes scale ranging from 40k to 2 million. Experimental results show that compared with the conventional TICER, the proposed P- TICER is up to 24 times faster, while achieving a node compression ratio up to 50% with the relative error remained within 0.2%.