Node predicting based direct cache coherence protocol for chip multi-processor

The performance promotion of modern processor depends on the excavation of memory system. Along with the booming of cores integrated in chip and the continual shrink of critical size, the cache coherence protocol with good scalability of latency and memory overhead has become the key factor to increase the memory access efficiency. This paper proposes a node predicting based direct cache coherence protocol-NPP, which mainly focuses on the research of techniques for cache coherence transaction latency hiding and memory overhead reduction. To solve the indirection problem in read/write miss transaction and overcome the shortcomings of data locality broken and inability to get the nearest valid copy in existing proposals, we propose the node hanging technique and direct write-miss processing technique to hide the directory access latency in read miss and write miss. In addition, we also propose a signature collection based history information update algorithm to avoid the superfluous or incomplete update. Simulation results show that for a 2D MESH NoC based 64-core CMP, compared to flat full map directory protocol, NPP reduces average execution time by 21.78%~31.11%, average read miss latency by 14.22%~18.9% and average write miss latency by 17.89%~21.13%. Besides the above performance promotion, price of NPP is increasing of on-chip network traffic by 6.62%~7.28% on average.