High-speed and memory-efficient VLSI design of 2D DWT for JPEG2000

K. Mei; N. Zheng; H. Van De Wetering

doi:10.1049/el:20061551

High-speed and memory-efficient VLSI design of 2D DWT for JPEG2000

K. Mei
, N. Zheng
, H. Van De Wetering

人工智能学院

Xi'an Jiaotong University
Eindhoven University of Technology

科研成果: 期刊稿件 › 文章 › 同行评审

5 引用（Scopus）

摘要

A highly pipelined line-based one-level 2D discrete wavelet transform (DWT) VLSI design is proposed using two line-FIFOs in 5/3 wavelet type and performing with input speed up to 2 samples/cycle. Furthermore, a recursive multi-level wavelet decomposition architecture using a dual buffer scheme is proposed to reduce the memory for wavelet coefficients to 1/4 Tile size. The two proposals allow for a 2D DWT architecture for JPEG2000 that is both high-speed and memory-efficient.

源语言	英语
页（从-至）	907-908
页数	2
期刊	Electronics Letters
卷	42
期	16
DOI	https://doi.org/10.1049/el:20061551
出版状态	已出版 - 3 8月 2006

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High-speed and memory-efficient VLSI design of 2D DWT for JPEG2000

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