TY - GEN
T1 - Full-CDAC Background Calibration Leveraging Bridge-crossing Shuffling for a 1.8 MS/s 20-bit SAR ADC
AU - Yang, Xunhua
AU - Ji, Junyao
AU - Jiao, Zihao
AU - Hu, Senran
AU - Wang, Xiaofei
AU - Zhang, Hong
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - This paper presents a signal-independent background calibration scheme for a 20-bit 1.8 MS/s SAR ADC, which includes 4 swapping capacitor pairs (SCPs) added into 5 clusters in the 3-segment CDAC. Double conversion is performed for each sample with VREFP or VREFN alternately applied to the SCP, thus the capacitor mismatch can be exposed in the difference (ΔD) of the two results. Assisted by pseudo-randomized bridge-crossing shuffling of the 5 clusters, the weights for the full CDAC are calibrated by an on-chip digital LMS engine using ΔD as its input in the background. Once the calibration has converged, the 2nd conversion can be skipped to improve the conversion speed. Designed in 180-nm CMOS, the ADC achieves a SNDR of 101dB and a SFDR of 120dB at a sampling rate of 1.8 MS/s, with a FoM of 178.5 dB in the normal operation mode after calibration.
AB - This paper presents a signal-independent background calibration scheme for a 20-bit 1.8 MS/s SAR ADC, which includes 4 swapping capacitor pairs (SCPs) added into 5 clusters in the 3-segment CDAC. Double conversion is performed for each sample with VREFP or VREFN alternately applied to the SCP, thus the capacitor mismatch can be exposed in the difference (ΔD) of the two results. Assisted by pseudo-randomized bridge-crossing shuffling of the 5 clusters, the weights for the full CDAC are calibrated by an on-chip digital LMS engine using ΔD as its input in the background. Once the calibration has converged, the 2nd conversion can be skipped to improve the conversion speed. Designed in 180-nm CMOS, the ADC achieves a SNDR of 101dB and a SFDR of 120dB at a sampling rate of 1.8 MS/s, with a FoM of 178.5 dB in the normal operation mode after calibration.
KW - 3-segment CDAC
KW - bridge-crossing shuffling
KW - full-CDAC calibration
KW - SAR ADC
KW - swapping capacitor pair
UR - https://www.scopus.com/pages/publications/105034648409
U2 - 10.1109/ICTA68203.2025.11330142
DO - 10.1109/ICTA68203.2025.11330142
M3 - 会议稿件
AN - SCOPUS:105034648409
T3 - 2025 IEEE 8th International Conference on Integrated Circuits, Technologies and Applications, ICTA 2025
SP - 33
EP - 34
BT - 2025 IEEE 8th International Conference on Integrated Circuits, Technologies and Applications, ICTA 2025
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2025 IEEE 8th International Conference on Integrated Circuits, Technologies, and Applications, ICTA2025
Y2 - 22 October 2025 through 24 October 2025
ER -