TY - JOUR
T1 - Exploring the use of emerging nonvolatile memory technologies in future FPGAs
AU - Pan, Yangyang
AU - Li, Yiran
AU - Sun, Hongbin
AU - Xu, Wei
AU - Zheng, Nanning
AU - Zhang, Tong
PY - 2013
Y1 - 2013
N2 - As new nonvolatile memory technologies become increasingly mature, there has been a growing interest on investigating their use in future field-programmable gate arrays (FPGAs). Similar to existing FPGAs with embedded Flash memory, future FPGAs can embed these new nonvolatile memories to persistently store configuration data. By comparing with prior work, we first propose the more appropriate design style for new nonvolatile configuration data storage memory. Moreover, this brief studies a dynamic random-access memory (DRAM)-based FPGA design strategy enabled by high-density embedded nonvolatile memory. Existing FPGAs do not use on-chip DRAM cells for configuration data storage mainly because DRAM self-refresh involves destructive DRAM read. This problem can be solved, if we use embedded nonvolatile memory as primary FPGA configuration data storage and externally refresh on-chip DRAM cells. Analysis and simulations have been carried out to demonstrate the potential advantages of such a design strategy.
AB - As new nonvolatile memory technologies become increasingly mature, there has been a growing interest on investigating their use in future field-programmable gate arrays (FPGAs). Similar to existing FPGAs with embedded Flash memory, future FPGAs can embed these new nonvolatile memories to persistently store configuration data. By comparing with prior work, we first propose the more appropriate design style for new nonvolatile configuration data storage memory. Moreover, this brief studies a dynamic random-access memory (DRAM)-based FPGA design strategy enabled by high-density embedded nonvolatile memory. Existing FPGAs do not use on-chip DRAM cells for configuration data storage mainly because DRAM self-refresh involves destructive DRAM read. This problem can be solved, if we use embedded nonvolatile memory as primary FPGA configuration data storage and externally refresh on-chip DRAM cells. Analysis and simulations have been carried out to demonstrate the potential advantages of such a design strategy.
KW - Dynamic random-access memory (DRAM)
KW - field-programmable gate arrays (FPGA)
KW - magnetoresistive random-access memory (MRAM)
KW - nonvolatile memory
UR - https://www.scopus.com/pages/publications/84875581442
U2 - 10.1109/TVLSI.2012.2195786
DO - 10.1109/TVLSI.2012.2195786
M3 - 文章
AN - SCOPUS:84875581442
SN - 1063-8210
VL - 21
SP - 771
EP - 775
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 4
M1 - 6198907
ER -