Energy and area efficient signal processing circuits using planar embedded DRAM

This paper studies the feasibility and potential of using planar embedded DRAM (eDRAM), which is completely compatible with CMOS logic process, to improve circuit implementation efficiency of signal processing algorithms. In spite of its apparent cell area efficiency advantage over SRAM, planar eDRAM is not being widely used in practice mainly due to its very short retention time. In this work, we contend that short retention time may not necessarily be a fundamental issue for implementing signal processing algorithms because they typically handle streaming data, exhibit regular and predictable data access pattern, and have large algorithm/architecture design space. This paper elaborates on the rationale and application using planar eDRAM in signal processing circuit implementations. For the purpose of demonstration, we use low-density parity-check (LDPC) code decoding as the test vehicle. Beyond straightforward SRAM replacement, we propose an interleaved read/write pagemode DRAM operation to reduce planar eDRAM energy consumption by leveraging LDPC code decoding data access pattern. We carried out detailed planar eDRAM SPICE simulations at 45nm node to obtain its characteristics, based on which we quantitatively evaluate the effectiveness of using planar eDRAM in this case study.