Efficient pipeline design of JPEG2000 encoder with low memory

An efficient JPEG2000 encoder is proposed and implemented with high pipeline and low memory architecture. Dual buffers to save the wavelet coefficients, pre-rate allocation and byte expression for Rate-Distortion (RD) slope are used to reduce on-chip memory size. Pipeline and parallel architecture is used in Discrete Wavelet Transform (DWT), Bit-Plane Encoder (BPE) and Arithmetic Encoder (AE) to increase the part circuit's encoding speed, searching the truncated RD slope in byte address space increases the packet formatting speed of Tier2. Problems met in system implementation such as clock distribution, SDRAM control of frame buffer and chrominance-transformation are also designed with optimization. The encoder is verified on FPGA platform. Performance of the encoder is as follows: the size of tile is up to 256 × 256 with code block in size of 32 × 32, input sampling rate is up to 45Msamples/s when Tierl is working at the clock of 100 MHz, difference of the PSNR of images compressed by the proposed encoder and JASPER is less than 0.5 dB at the rate of 0.4 bit per sample (bps). Equivalent gates synthesized are about 109k and on-chip RAM is 862 kb.