TY - JOUR
T1 - Dual-embedded cooling for thermoelectric coolers in electronics thermal management
AU - Du, Xiangbin
AU - Kong, Yanmei
AU - Ye, Yuxin
AU - Zhu, Hangtian
AU - Liu, Ruiwen
AU - Zhang, Guohe
AU - Yun, Shichang
AU - Jiao, Binbin
N1 - Publisher Copyright:
© 2025
PY - 2025/12/15
Y1 - 2025/12/15
N2 - Optimizing thermoelectric cooler (TECs) efficiency and cooling capacity requires minimizing the temperature difference between cold and hot sides. However, the parasitic thermal resistance induced by thermal interface materials in the conventional integration of TEC-based cooling systems elevates temperature difference, compromising their performance under rated power conditions. This study demonstrates a dual-embedded thermal module that integrates thermoelectric legs on the chip backside (serving as the TEC cold side) and embeds microfluidic channels into the substrate of hot side (functioning as the TEC hot side). A silicon test chip with integrated temperature sensors and heating functions was utilized to evaluate cooling performance. Compared to the TEC cooling module with conventional integration, the proposed design achieves a 33% enhancement in coefficient of performance (COP), a 61% reduction in total thermal resistance under equivalent cooling conditions, and a 47% decrease in the proportion of additional thermal resistance outside the TEC in the module. In addition, a prediction model was developed to quantify the impact of parasitic thermal resistance on the maximum achievable cooling power under varying loads. The dual-embedded cooling module demonstrates simultaneous enhancements of 66% in cooling power and 27.2% in temperature difference compared to conventional thermal solutions under equivalent thermal boundary conditions. This co-designed architecture eliminates thermal interface materials, slashing parasitic thermal resistance across heat transfer pathways, while bypassing complex heterogeneous integration challenges between TEC substrates and silicon chips, thereby ensuring reliable TEC performance maximization for high-flux electronics cooling.
AB - Optimizing thermoelectric cooler (TECs) efficiency and cooling capacity requires minimizing the temperature difference between cold and hot sides. However, the parasitic thermal resistance induced by thermal interface materials in the conventional integration of TEC-based cooling systems elevates temperature difference, compromising their performance under rated power conditions. This study demonstrates a dual-embedded thermal module that integrates thermoelectric legs on the chip backside (serving as the TEC cold side) and embeds microfluidic channels into the substrate of hot side (functioning as the TEC hot side). A silicon test chip with integrated temperature sensors and heating functions was utilized to evaluate cooling performance. Compared to the TEC cooling module with conventional integration, the proposed design achieves a 33% enhancement in coefficient of performance (COP), a 61% reduction in total thermal resistance under equivalent cooling conditions, and a 47% decrease in the proportion of additional thermal resistance outside the TEC in the module. In addition, a prediction model was developed to quantify the impact of parasitic thermal resistance on the maximum achievable cooling power under varying loads. The dual-embedded cooling module demonstrates simultaneous enhancements of 66% in cooling power and 27.2% in temperature difference compared to conventional thermal solutions under equivalent thermal boundary conditions. This co-designed architecture eliminates thermal interface materials, slashing parasitic thermal resistance across heat transfer pathways, while bypassing complex heterogeneous integration challenges between TEC substrates and silicon chips, thereby ensuring reliable TEC performance maximization for high-flux electronics cooling.
KW - Embedded cooling
KW - Microchannel
KW - Parasitic thermal resistance
KW - Thermoelectric
UR - https://www.scopus.com/pages/publications/105018308877
U2 - 10.1016/j.applthermaleng.2025.128568
DO - 10.1016/j.applthermaleng.2025.128568
M3 - 文章
AN - SCOPUS:105018308877
SN - 1359-4311
VL - 281
JO - Applied Thermal Engineering
JF - Applied Thermal Engineering
M1 - 128568
ER -