Design of high speed arithmetic encoder

Focusing on the problem of path waiting or circular that existed in updating of context table and the Renorme and Byteout procedure in the realization of the conventional arithmetic encoder in JPEG2000, 3-step pipeline architecture is used on FPGA to get high speed encoding. A method of updating CX table is proposed; and a circuit with short delay is also implemented to detect the left zeros of A-register. Multiplexers are adopted to accelerate the random left shift operation, and parallel processing based on data dependency is used to optimize RTL code to shorten the main critical path, the updating logic of context table is last fully discussed. Experimental result shows the encoder can work up to 107MHz on Altera's EP1S25B672C7 and the critical path is 4.6 ns synthesized in synopsys DC by TSMC.25um library.