Design of digital filter used in embedded measuring system of PD

In the embedded measuring system for partial discharge (PD) signals based on FPGA, a new method was introduced to suppress the periodical noises. According to the principle of FIR digital filter, models for simulating and calculating were developed with the toolboxes of Simulink and DSP Builder in the Matlab software. The coefficients of filter can be calculated according to the users' configuration. In order to simulate the PD signals with noises in the field detection, PD occurred in a single void was simulated and then mixed with noises of high and low frequencies. The PD signals with noises were introduced in the filter's model. Then, the model was converted into RTL codes in the form of VHDL or Verilog HDL which could be used in the embedded system. This design method is proved to be feasible in the process of design, conversion, and verification. Comparing with the conventional methods to encode one and more adders or multiplicators with low-level language, this method can simplify the developing steps, reduce the difficulty and shorten developing period. More importantly, models built with this method can be easily configured and modified, and RTL codes created by dsp Builder also have better performance. This design shows a good usage of the modern digital processing technology in the electrical engineering, especially in the PD measurement.