Design and implementation of Radix-8 complex divider

A Radix-8 complex divider with high performance and low power is designed. The complex divider architecture adopts the digit-recurrence algorithm and the prescaling technique of operands, and has an optimizing function, with which the prescaled operands are kept in redundant forms so that long carry propagation adders are saved. Moreover, combination of the real and imaginary parts of the internal quotient digits and optimization for hardware mapping based on the 6-input look-up table are made to improve the utilization of logic resources. The proposed design is then implemented on Stratix-II field programmable gate array. Simulation results and comparisons with the traditional structure show that the speed of the complex divider is increased by 44% and its hardware resources are reduced by 31%.