Design and implementation of a mixed-signal boost converter with a novel multi-phase clock DPWM

There exists a trade-off among resolution, area and power losses in controllers of switching DC-DC converters. In this letter, a mixed-signal Boost converter topology is presented to lower the resolution requirements of ADC and DPWM. In addition, by using time-multiplexing technology, a novel multi-phase clock DPWM is proposed. Design Compiler synthesis results indict that, compared with normal 1-phase clock DPWM, chip area and power consumption of the proposed 4-phase clock DPWM is reduced by 47.0% and 54.4%, respectively. The new DPWM is realized using FPGA and applied in a prototype Boost converter. Experimental results verify the functionality of the optimized DPWM.