TY - GEN
T1 - Design and Implementation of a Low-Voltage-Stress DC Impedance Measurement Device Featuring DC-Blocking Capacitive Voltage Division
AU - Liu, Banghong
AU - Wang, Haixu
AU - Ma, Ruihan
AU - Dai, Yuqi
AU - Lei, Wanjun
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - The proliferation of power electronic devices in DC distribution networks, compounded by inherent supply instability and significant load fluctuations, presents substantial challenges for system stability analysis. As impedance analysis - the most expedient and widely adopted stability assessment method - requires prior knowledge of grid-connected equipment impedance characteristics, this paper investigates a DC-blocking capacitive divider-based impedance measurement apparatus with low voltage stress. This article proposes a topology of a DC distribution network impedance measurement device that can effectively reduce the voltage stress on the switching devices of a single-phase full-bridge inverter, enhance the effective modulation ratio of the device, and achieve electrical isolation between high and low voltages, allowing the disturbance source to exhibit current source characteristics. Subsequent analysis quantifies the proposed topology's advantages over conventional solutions through comparative assessment of loop gain and modulation performance. Finally, an impedance measurement prototype was implemented, with experimental results demonstrating close agreement between measured impedance characteristics and theoretical predictions.
AB - The proliferation of power electronic devices in DC distribution networks, compounded by inherent supply instability and significant load fluctuations, presents substantial challenges for system stability analysis. As impedance analysis - the most expedient and widely adopted stability assessment method - requires prior knowledge of grid-connected equipment impedance characteristics, this paper investigates a DC-blocking capacitive divider-based impedance measurement apparatus with low voltage stress. This article proposes a topology of a DC distribution network impedance measurement device that can effectively reduce the voltage stress on the switching devices of a single-phase full-bridge inverter, enhance the effective modulation ratio of the device, and achieve electrical isolation between high and low voltages, allowing the disturbance source to exhibit current source characteristics. Subsequent analysis quantifies the proposed topology's advantages over conventional solutions through comparative assessment of loop gain and modulation performance. Finally, an impedance measurement prototype was implemented, with experimental results demonstrating close agreement between measured impedance characteristics and theoretical predictions.
KW - DC Power Systems
KW - Impedance Measurement
KW - Low-Voltage-Stress
KW - Single-Phase Full-Bridge Inverters
UR - https://www.scopus.com/pages/publications/105035915918
U2 - 10.1109/PEAS66638.2025.11403050
DO - 10.1109/PEAS66638.2025.11403050
M3 - 会议稿件
AN - SCOPUS:105035915918
T3 - IEEE PEAS 2025 - 2025 IEEE 3rd International Power Electronics and Application Symposium - Conference Proceedings
SP - 1808
EP - 1815
BT - IEEE PEAS 2025 - 2025 IEEE 3rd International Power Electronics and Application Symposium - Conference Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2025 IEEE 3rd International Power Electronics and Application Symposium, PEAS 2025
Y2 - 7 November 2025 through 10 November 2025
ER -