DC Fault Analysis Models of Three Converter Topologies Considering Control Effects

Existing converter models are normally reduced as simplified electrical components, whereas it overlooks the impacts of fast dynamics of converter current control loops. Therefore, the dc fault current calculation with the traditional simplified converter models becomes invalid when the simulation time is longer. To overcome this problem, this article incorporates the control effects of converters during the transient process and proposes three dc fault analysis models of classical three converter topologies for the high-voltage dc (HVdc) application including line communicated converter (LCC), two-level voltage-source converter (VSC), and modular multilevel converter (MMC). For an LCC-based rectifier, the nonlinear part of original model is first linearized with the least square method due to the large dc-link voltage deviation during dc fault, and the proportional integral (PI) current regulator with the reduced linearized model can be equivalent as an RC circuit for dc fault analysis. However, for two-level VSC or MMC, the dc-link voltage deviation does not drop that much with a large dc-link capacitor discharging process during transient dynamics. As a result, the original model is linearized relying on the small-signal method based on prefault operation points, and the dynamics of fast inner current loop with the linearized model can be represented as an RL circuit for dc fault current calculation. for dc fault analysis The proposed dc fault analysis models of three converters as equivalent RLC circuits are well testified under different fault resistances and dc reactors, control parameters, and operating conditions. Moreover, dc fault simulations of a hybrid HVdc system have verified the effectiveness of the proposed converter models.