TY - JOUR
T1 - Analysis and suppression of inductive interference in an active integrated power electronics module
AU - Chen, Qiaoliang
AU - Pei, Yunqing
AU - Yang, Xu
AU - Wang, Zhaoan
PY - 2009/12
Y1 - 2009/12
N2 - The interference between the power stage and the driving circuit is one of the key issues of power module design, especially for those with high power densities, where couplings become more severe. This paper focuses on suppression techniques for inductive coupling. As a demonstration, a 2 kW single phase power factor correction active integrated power electronic module consisting of full bridge rectifiers, a current sensing resistor, and boost converter, is developed employing CoolMOS FET and SiC diodes. The electromagnetic interference mechanism in the module is analyzed and illustrated. In order to reduce the voltage spike of the power devices, three different design patterns of the power stage layout are presented and compared with regard to the reduction of parasitic self-inductance of the critical loop in the power stage. The approaches to reducing the inductive interference between the high di/dt loop in the power stage and the driving loop are investigated, including the proposed flux cancelation pattern for the layout of the high power di/dt loop, reduction of electromagnetic interference sources, and the insertion of a copper shielding layer between them. Finally, the design guidelines are built and verified by the simulation and experimental results.
AB - The interference between the power stage and the driving circuit is one of the key issues of power module design, especially for those with high power densities, where couplings become more severe. This paper focuses on suppression techniques for inductive coupling. As a demonstration, a 2 kW single phase power factor correction active integrated power electronic module consisting of full bridge rectifiers, a current sensing resistor, and boost converter, is developed employing CoolMOS FET and SiC diodes. The electromagnetic interference mechanism in the module is analyzed and illustrated. In order to reduce the voltage spike of the power devices, three different design patterns of the power stage layout are presented and compared with regard to the reduction of parasitic self-inductance of the critical loop in the power stage. The approaches to reducing the inductive interference between the high di/dt loop in the power stage and the driving loop are investigated, including the proposed flux cancelation pattern for the layout of the high power di/dt loop, reduction of electromagnetic interference sources, and the insertion of a copper shielding layer between them. Finally, the design guidelines are built and verified by the simulation and experimental results.
KW - Electromagnetic interference
KW - Inductive interference
KW - Integrated power electronic modules
KW - Partial elements equivalent circuit
UR - https://www.scopus.com/pages/publications/72149098570
U2 - 10.1109/TCAPT.2009.2029085
DO - 10.1109/TCAPT.2009.2029085
M3 - 文章
AN - SCOPUS:72149098570
SN - 1521-3331
VL - 32
SP - 724
EP - 733
JO - IEEE Transactions on Components and Packaging Technologies
JF - IEEE Transactions on Components and Packaging Technologies
IS - 4
M1 - 5286853
ER -