TY - JOUR
T1 - Analysis and Flexible DV/DT Control of an Active Clamping Topology for Series-Connected SiC MOSFETs
AU - Zhang, Fan
AU - Zheng, Yuze
AU - Zhang, Xuan
AU - Yang, Xu
AU - Chen, Wenjie
N1 - Publisher Copyright:
© 1986-2012 IEEE.
PY - 2023/4/1
Y1 - 2023/4/1
N2 - Series-connection of SiC mosfets is an attractive solution to build cost effective and high efficiency medium voltage converters, however, the unequal voltage sharing among the power devices and the induced high dv/dt problems should be considered carefully. In this article, an active clamping topology and corresponding dv/dt control method for series-connected SiC mosfets are proposed. With the proposed topology, the drain-source voltage of each SiC mosfet can be clamped by discrete clamping capacitor, resulting in high robust switching. Besides, the clamping capacitor voltages can be autobalanced during the topology operation, so the peak voltages of the series-connected SiC mosfets can be easily balanced. By simply adjusting the gate drive delay time, the proposed topology could reduce the equivalent dv/dt of the device string with very small increase in power loss, so the high dv/dt induced switching noise can be suppressed greatly. Finally, a 4.8 kV/10 A half-bridge prototype is established with six SiC mosfets connected in series within per bridge arm, experimental results are provided to show the effectiveness and advancement of the proposed method.
AB - Series-connection of SiC mosfets is an attractive solution to build cost effective and high efficiency medium voltage converters, however, the unequal voltage sharing among the power devices and the induced high dv/dt problems should be considered carefully. In this article, an active clamping topology and corresponding dv/dt control method for series-connected SiC mosfets are proposed. With the proposed topology, the drain-source voltage of each SiC mosfet can be clamped by discrete clamping capacitor, resulting in high robust switching. Besides, the clamping capacitor voltages can be autobalanced during the topology operation, so the peak voltages of the series-connected SiC mosfets can be easily balanced. By simply adjusting the gate drive delay time, the proposed topology could reduce the equivalent dv/dt of the device string with very small increase in power loss, so the high dv/dt induced switching noise can be suppressed greatly. Finally, a 4.8 kV/10 A half-bridge prototype is established with six SiC mosfets connected in series within per bridge arm, experimental results are provided to show the effectiveness and advancement of the proposed method.
KW - DV/DT control
KW - SiC MOSFET
KW - series-connection
KW - voltage balancing
UR - https://www.scopus.com/pages/publications/85147215176
U2 - 10.1109/TPEL.2022.3233725
DO - 10.1109/TPEL.2022.3233725
M3 - 文章
AN - SCOPUS:85147215176
SN - 0885-8993
VL - 38
SP - 4840
EP - 4855
JO - IEEE Transactions on Power Electronics
JF - IEEE Transactions on Power Electronics
IS - 4
ER -