Analysis and design of monolithic DC/DC converters

Qing Hua Li; Zhi Biao Shao; Li Geng

Analysis and design of monolithic DC/DC converters

Qing Hua Li
, Zhi Biao Shao
, Li Geng

电子与信息学部

Xi'an Jiaotong University

科研成果: 期刊稿件 › 文章 › 同行评审

1 引用（Scopus）

摘要

The challenges and tradeoffs in designing a monolithic DC/DC converter including planner inductor using 0.35 μm CMOS technology on silicon substrate are described by analyzing the power dissipation of the converters. The efficiency of the converter is optimized. The physical design and geometric parameters optimization of the desired planar inductor are given. A double-layer spiral inductor with quality factor of 2.3, area of 0.38 square millimeters, inductance of 35 nH are obtained. From the simulated results, a steady Buck converter with the efficiency of 62% is achieved.

源语言	英语
页（从-至）	65-67+73
期刊	Dianzi Keji Daxue Xuebao/Journal of the University of Electronic Science and Technology of China
卷	37
期	1
出版状态	已出版 - 1月 2008

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abstract = "The challenges and tradeoffs in designing a monolithic DC/DC converter including planner inductor using 0.35 μm CMOS technology on silicon substrate are described by analyzing the power dissipation of the converters. The efficiency of the converter is optimized. The physical design and geometric parameters optimization of the desired planar inductor are given. A double-layer spiral inductor with quality factor of 2.3, area of 0.38 square millimeters, inductance of 35 nH are obtained. From the simulated results, a steady Buck converter with the efficiency of 62\% is achieved.",

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AB - The challenges and tradeoffs in designing a monolithic DC/DC converter including planner inductor using 0.35 μm CMOS technology on silicon substrate are described by analyzing the power dissipation of the converters. The efficiency of the converter is optimized. The physical design and geometric parameters optimization of the desired planar inductor are given. A double-layer spiral inductor with quality factor of 2.3, area of 0.38 square millimeters, inductance of 35 nH are obtained. From the simulated results, a steady Buck converter with the efficiency of 62% is achieved.

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KW - Efficiency

KW - Monolithic

KW - Planar inductor

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Analysis and design of monolithic DC/DC converters

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