An improved line-drawing algorithm for arbitrary fractional frequency divider/multiplier based on FPGA

The proposed algorithm aims to realize the division of arbitrary fractional frequency. The general frequency divider is comprised of the counter cascade, and can realize the even frequency division easily, but it is difficult to realize odd frequency divider and fractional frequency divider. This paper proposes a design method of Arbitrary Fractional Frequency Divider (AFFD)based on FPGA circuit cores by an improved Bresenham line-drawing algorithm, which reduces the hardware resource and eases the implementation process. Bresenham line-drawing algorithm is introduced briefly in this paper outside its original applications. The circuit is designed with Verilog Hard Design Language(VHDL), and the program is proposed. The frequency divider is simulated in Quartus II and the divider is examined in FPGABased gear hobbling machine CNC system to control the step-servo motor, and the result is steady and reliable. This paper extends the investigation on the frequency division by the improved algorithm. The algorithm designs arbitrary Fractional Frequency Multiplier, and it is also examined by simulation and experiment.