All digital phase‐locked loop with nonlinear multilevel quantized phase comparator

The PLL has assumed an important role and is widely employed in communication systems. In recent years efforts have been directed toward implementation of PLLs by means of digital circuitry and a large number of digital PLLs (DPLLs) have been reported. the binary quantized DPLL has received particular attention. However, in a first‐order PLL, pull‐in performance and operation in the lock mode have conflicting requirements and, in addition, a steadyphase difference is produced when the input signal has a frequency offset, resulting in unfavorable effects on the communication system. In the past, these problems have been resolved by employing a second‐order loop but, due to the resultant complexity of the loop, this causes several problems, including poor transient response and integrator drift. In this paper we present a new DPLL incorporating a nonlinear multilevel quantized phase comparator (with characteristic τ sgn ψ ‐ ψ). By means of its phase comparator characteristic this loop improves the steady‐state phase error and also affords more rapid transient response as well as other features including excellent jitter suppression within the pull‐in range. Performance characteristics of the proposed loop are determined theoretically and are verified by experiment.