A power-delay-product efficient and SEU-tolerant latch design

With the increasing high requirements for digital circuits in space application, devices with smaller feature size are put into use, which have more potential suffering from Single Event Upset (SEU) under certain radiation environment. In this paper, we propose a SEU-tolerant latch with low power-delay-product (PDP) that combines a SEU-tolerant cross-coupled structure with isolation operation of flipped state. Negative feedback paths are introduced to help recover the flipped state and can be cut off to speed up the write operation at transparent mode. Furthermore, isolation of flipped state is utilized to achieve better SEU-tolerance. The simulation results with 180 nm and 40 nm CMOS technology show that the proposed latch can achieve outstanding SEU-tolerance (Q_critical > 10 fC) and a relatively low PDP of 0.0095 fs×J for 40 nm CMOS technology.