A low-noise readout ASIC with nonlinearity compensated pseudo-differential charge-balanced CV converter for MEMS capacitive accelerometers

This paper presents a low-noise, highly integrated readout ASIC with a pseudo-differential charge-balanced C-V converter (CVC) for MEMS capacitive accelerometers. Assisted by a 4-phase clock scheme, the CVC performs pseudo-differential processing of the single-ended output signal from the sensing element, thereby suppressing the sensor-originated common-mode (CM) interference and bias drift, while enhancing immunity to supply noise and electromagnetic interference (EMI). Based on a theoretical analysis of nonlinearity caused by the parasitic capacitance parallel to the main sensing capacitor bridge, a compensation capacitor array with opposite charging polarity is added to the CVC to cancel the effect of the parasitic capacitance, thereby significantly improving the linearity. A 3rd-order ΔΣ ADC is integrated in the ASIC to convert the CVC's output into digits, while digital temperature compensation is performed with the assistance of an on-chip temperature sensor. Fabricated in a 0.18-μm CMOS process, the ASIC consumes a total power of 3.63 mW. Measurement results show that the system achieves a dynamic range of 95.47 dB across a 200-Hz bandwidth and offers a sensitivity of 80 mV/g, while showing an outstanding nonlinearity of only 1.77‰ before digital nonlinearity calibration over the input range of ±30 g, a bias drift of 0.77 mg/°C before digital temperature calibration in the range of −40 °C to 125 °C, and a bias instability of 31.57 μg. The figure of merit (FoM) is 305.76 pJ.