A low-inductance packaging layout for 1.2kV, 40A Full-SiC power module embedding split damping capacitors

Yu Ren; Fan Zhang; Long Liu; Linlin Tan; Xu Yang; Xiangjun Zeng

doi:10.1109/IFEEC.2015.7361520

A low-inductance packaging layout for 1.2kV, 40A Full-SiC power module embedding split damping capacitors

Yu Ren
, Fan Zhang
, Long Liu
, Linlin Tan
, Xu Yang
, Xiangjun Zeng

电气工程学院

Xi'an Jiaotong University

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

1 引用（Scopus）

摘要

A novel packaging layout of Full-SiC(Silicon Carbide) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) Module with split damping capacitors embedding inside innovatively is proposed, which decrease stray inductance greatly. Since the stray inductance of the commutation loop caused by bonding wires and patterns on the substrate will result in a large voltage spike over the semiconductor device. The module with damping capacitors inside will decrease the stray inductance of the commutation loop significantly. The stray inductance extracted by commercial simulation software ANSYS Q3D Extractor electromagnetic FEA (Finite Element Analysis) tool show that a total self-inductance of the single commutation loop is 6.2nH. The LTspice simulation based on the synchronous buck circuit shows a 55V voltage spike over the semiconductor on the current rate 6717A/μs. In this paper, the current difference between two parallel branches is simulated by LTspice and a remarkable performance is observed. These results demonstrate the validity of the proposed packaging structure of a Full-SiC Module.

源语言	英语
主期刊名	2015 IEEE 2nd International Future Energy Electronics Conference, IFEEC 2015
出版商	Institute of Electrical and Electronics Engineers Inc.
ISBN（电子版）	9781479976577
DOI	https://doi.org/10.1109/IFEEC.2015.7361520
出版状态	已出版 - 18 12月 2015
活动	2nd IEEE International Future Energy Electronics Conference, IFEEC 2015 - Taipei, 中国台湾期限: 1 11月 2015 → 4 11月 2015

出版系列

姓名	2015 IEEE 2nd International Future Energy Electronics Conference, IFEEC 2015

会议

会议	2nd IEEE International Future Energy Electronics Conference, IFEEC 2015
国家/地区	中国台湾
市	Taipei
时期	1/11/15 → 4/11/15

联合国可持续发展目标

此成果有助于实现下列可持续发展目标：

可持续发展目标 7 经济适用的清洁能源

访问文件

10.1109/IFEEC.2015.7361520

其它文件与链接

链接到 Scopus 的出版物

引用此

Ren, Y., Zhang, F., Liu, L., Tan, L., Yang, X., & Zeng, X. (2015). A low-inductance packaging layout for 1.2kV, 40A Full-SiC power module embedding split damping capacitors. 在 2015 IEEE 2nd International Future Energy Electronics Conference, IFEEC 2015 文章 7361520 (2015 IEEE 2nd International Future Energy Electronics Conference, IFEEC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IFEEC.2015.7361520

@inproceedings{275d0f72abf948c58d2524c87c722e2d,

title = "A low-inductance packaging layout for 1.2kV, 40A Full-SiC power module embedding split damping capacitors",

abstract = "A novel packaging layout of Full-SiC(Silicon Carbide) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) Module with split damping capacitors embedding inside innovatively is proposed, which decrease stray inductance greatly. Since the stray inductance of the commutation loop caused by bonding wires and patterns on the substrate will result in a large voltage spike over the semiconductor device. The module with damping capacitors inside will decrease the stray inductance of the commutation loop significantly. The stray inductance extracted by commercial simulation software ANSYS Q3D Extractor electromagnetic FEA (Finite Element Analysis) tool show that a total self-inductance of the single commutation loop is 6.2nH. The LTspice simulation based on the synchronous buck circuit shows a 55V voltage spike over the semiconductor on the current rate 6717A/μs. In this paper, the current difference between two parallel branches is simulated by LTspice and a remarkable performance is observed. These results demonstrate the validity of the proposed packaging structure of a Full-SiC Module.",

author = "Yu Ren and Fan Zhang and Long Liu and Linlin Tan and Xu Yang and Xiangjun Zeng",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 2nd IEEE International Future Energy Electronics Conference, IFEEC 2015 ; Conference date: 01-11-2015 Through 04-11-2015",

year = "2015",

month = dec,

day = "18",

doi = "10.1109/IFEEC.2015.7361520",

language = "英语",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Ren, Y, Zhang, F, Liu, L, Tan, L, Yang, X & Zeng, X 2015, A low-inductance packaging layout for 1.2kV, 40A Full-SiC power module embedding split damping capacitors. 在 2015 IEEE 2nd International Future Energy Electronics Conference, IFEEC 2015., 7361520, 2015 IEEE 2nd International Future Energy Electronics Conference, IFEEC 2015, Institute of Electrical and Electronics Engineers Inc., 2nd IEEE International Future Energy Electronics Conference, IFEEC 2015, Taipei, 中国台湾, 1/11/15. https://doi.org/10.1109/IFEEC.2015.7361520

A low-inductance packaging layout for 1.2kV, 40A Full-SiC power module embedding split damping capacitors. / Ren, Yu; Zhang, Fan; Liu, Long 等.
2015 IEEE 2nd International Future Energy Electronics Conference, IFEEC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7361520 (2015 IEEE 2nd International Future Energy Electronics Conference, IFEEC 2015).

科研成果: 书/报告/会议事项章节 › 会议稿件 › 同行评审

TY - GEN

T1 - A low-inductance packaging layout for 1.2kV, 40A Full-SiC power module embedding split damping capacitors

AU - Ren, Yu

AU - Zhang, Fan

AU - Liu, Long

AU - Tan, Linlin

AU - Yang, Xu

AU - Zeng, Xiangjun

PY - 2015/12/18

Y1 - 2015/12/18

N2 - A novel packaging layout of Full-SiC(Silicon Carbide) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) Module with split damping capacitors embedding inside innovatively is proposed, which decrease stray inductance greatly. Since the stray inductance of the commutation loop caused by bonding wires and patterns on the substrate will result in a large voltage spike over the semiconductor device. The module with damping capacitors inside will decrease the stray inductance of the commutation loop significantly. The stray inductance extracted by commercial simulation software ANSYS Q3D Extractor electromagnetic FEA (Finite Element Analysis) tool show that a total self-inductance of the single commutation loop is 6.2nH. The LTspice simulation based on the synchronous buck circuit shows a 55V voltage spike over the semiconductor on the current rate 6717A/μs. In this paper, the current difference between two parallel branches is simulated by LTspice and a remarkable performance is observed. These results demonstrate the validity of the proposed packaging structure of a Full-SiC Module.

AB - A novel packaging layout of Full-SiC(Silicon Carbide) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) Module with split damping capacitors embedding inside innovatively is proposed, which decrease stray inductance greatly. Since the stray inductance of the commutation loop caused by bonding wires and patterns on the substrate will result in a large voltage spike over the semiconductor device. The module with damping capacitors inside will decrease the stray inductance of the commutation loop significantly. The stray inductance extracted by commercial simulation software ANSYS Q3D Extractor electromagnetic FEA (Finite Element Analysis) tool show that a total self-inductance of the single commutation loop is 6.2nH. The LTspice simulation based on the synchronous buck circuit shows a 55V voltage spike over the semiconductor on the current rate 6717A/μs. In this paper, the current difference between two parallel branches is simulated by LTspice and a remarkable performance is observed. These results demonstrate the validity of the proposed packaging structure of a Full-SiC Module.

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BT - 2015 IEEE 2nd International Future Energy Electronics Conference, IFEEC 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2nd IEEE International Future Energy Electronics Conference, IFEEC 2015

Y2 - 1 November 2015 through 4 November 2015

ER -

Ren Y, Zhang F, Liu L, Tan L, Yang X, Zeng X. A low-inductance packaging layout for 1.2kV, 40A Full-SiC power module embedding split damping capacitors. 在 2015 IEEE 2nd International Future Energy Electronics Conference, IFEEC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. 7361520. (2015 IEEE 2nd International Future Energy Electronics Conference, IFEEC 2015). doi: 10.1109/IFEEC.2015.7361520

A low-inductance packaging layout for 1.2kV, 40A Full-SiC power module embedding split damping capacitors

摘要

出版系列

会议

联合国可持续发展目标

访问文件

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引用此