TY - GEN
T1 - A delay time controlled active rectifier with 95.3% peak efficiency for wireless power transmission systems
AU - Xue, Zhongming
AU - Li, Dan
AU - Gou, Wei
AU - Zhang, Lina
AU - Fan, Shiquan
AU - Geng, Li
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/9/25
Y1 - 2017/9/25
N2 - Active rectifier with comparators (CMPs) is often used in wireless power transmission (WPT) systems. However, it suffers from low power conversion efficiency (PCE) in light load condition and multiple pulse problem (MPP) due to the CMPs with delay compensation. In this paper, a novel active rectifier with delay time controller is proposed to solve both issues. A current control delay line (CCDL) is introduced to adjust the rising and the falling edges of the gate voltages of the NMOS (Fgns), controlled by a negative feedback loop consisting of a switched-capacitor (SC) sample module and a supply independent bias current controller (IB controller). The proposed rectifier is designed with a standard 0.18μm CMOS process. Post-layout simulation results show that the delay time controller consumes only 34μA, which is much smaller than the power consumptions induced by controller with CMPs, thus significantly enhancing the PCE of the rectifier. The PCE of the rectifier is higher than 88% in the whole load range from 629μA to 32.1mA, and exceeds 92% when load resistance Rl varies from 100Ω to 1200Ω. A peak PCE of 95.3% is achieved when Rl is 200Ω and Vac is 2V.
AB - Active rectifier with comparators (CMPs) is often used in wireless power transmission (WPT) systems. However, it suffers from low power conversion efficiency (PCE) in light load condition and multiple pulse problem (MPP) due to the CMPs with delay compensation. In this paper, a novel active rectifier with delay time controller is proposed to solve both issues. A current control delay line (CCDL) is introduced to adjust the rising and the falling edges of the gate voltages of the NMOS (Fgns), controlled by a negative feedback loop consisting of a switched-capacitor (SC) sample module and a supply independent bias current controller (IB controller). The proposed rectifier is designed with a standard 0.18μm CMOS process. Post-layout simulation results show that the delay time controller consumes only 34μA, which is much smaller than the power consumptions induced by controller with CMPs, thus significantly enhancing the PCE of the rectifier. The PCE of the rectifier is higher than 88% in the whole load range from 629μA to 32.1mA, and exceeds 92% when load resistance Rl varies from 100Ω to 1200Ω. A peak PCE of 95.3% is achieved when Rl is 200Ω and Vac is 2V.
KW - active rectifier
KW - current control delay Une
KW - delay time controller
KW - wireless power transmission
UR - https://www.scopus.com/pages/publications/85032672866
U2 - 10.1109/ISCAS.2017.8050846
DO - 10.1109/ISCAS.2017.8050846
M3 - 会议稿件
AN - SCOPUS:85032672866
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
Y2 - 28 May 2017 through 31 May 2017
ER -