TY - GEN
T1 - A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure
AU - Song, Yan
AU - Zhu, Yan
AU - Chan, Chi Hang
AU - Geng, Li
AU - Martins, Rui Paulo
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/10/22
Y1 - 2018/10/22
N2 - This paper presents a wide-band and energy-efficient 0-1 MASH ΣΔ ADC which is realized based on the pipelined-SAR structure. Composed by a 6b SAR ADC in the 1st-stage and a 5b SAR ADC in the 2nd-stage, with alternate loading capacitors (ALC) reused for error feedback, it realizes an ideal 1st-order noise shaping while simultaneously maintaining a high-speed pipeline operation. Fabricated in 65nm CMOS, the prototype consumes 4.5mW from a 1.2V supply with 77dB SNDR over 12.5MHz bandwidth, leading to a 171.5dB Schreier FoM.
AB - This paper presents a wide-band and energy-efficient 0-1 MASH ΣΔ ADC which is realized based on the pipelined-SAR structure. Composed by a 6b SAR ADC in the 1st-stage and a 5b SAR ADC in the 2nd-stage, with alternate loading capacitors (ALC) reused for error feedback, it realizes an ideal 1st-order noise shaping while simultaneously maintaining a high-speed pipeline operation. Fabricated in 65nm CMOS, the prototype consumes 4.5mW from a 1.2V supply with 77dB SNDR over 12.5MHz bandwidth, leading to a 171.5dB Schreier FoM.
UR - https://www.scopus.com/pages/publications/85056813465
U2 - 10.1109/VLSIC.2018.8502382
DO - 10.1109/VLSIC.2018.8502382
M3 - 会议稿件
AN - SCOPUS:85056813465
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - 203
EP - 204
BT - 2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
Y2 - 18 June 2018 through 22 June 2018
ER -