A 54-68 GHz Power Amplifier with Improved Linearity and Efficiency in 40 nm CMOS

This brief presents a 54-68 GHz two-stage power amplifier (PA) with linearity and efficiency enhancement in a 40 nm CMOS process. The first stage adopts a current reuse cascaded common-source (CS) structure with a shunt RC feedback to maximize the gain and minimize the DC power consumption to boost the linearity and efficiency, while the second stage is a cascode structure with two built-in linearizers to enhance the linearity much further. Based on the proposed structure, the fabricated PA exhibits measured output of 1-dB compression point, saturated output power, power added efficiency (PAE) and AM-PM distortion of +14 dBm, +15 dBm, 20% and 8 degrees, respectively. In addition, the proposed CMOS PA achieves high and flat power gain of 14 dB with ripple less than 1.5 dB through the operating 54 - 68 GHz frequency band while consuming only 110 mW.