TY - JOUR
T1 - A 4K × 2K@60fps multifunctional video display processor for high perceptual image quality
AU - Wang, Hang
AU - Li, Xiang
AU - Han, Daqiang
AU - Yu, Shiquan
AU - Yin, Shouyi
AU - Wei, Shaojun
AU - Zheng, Nanning
AU - Zhang, Xuchong
AU - Wang, Tiancheng
AU - Li, Wenchang
AU - Chen, Qiubo
AU - Ren, Pengju
AU - Wu, Xiaogang
AU - Sun, Hongbin
AU - Jiang, Zhiqiang
N1 - Publisher Copyright:
© 2004-2012 IEEE.
PY - 2020/2
Y1 - 2020/2
N2 - Video display processing is an indispensable module in a variety of multimedia systems. With the increase of video format to 4K × 2K@60fps, the design of efficient display processing circuit faces severe challenges. This paper presents a video display processor which supports a variety of video formats and integrates multiple advanced algorithms for perpetual image quality improvement. By leveraging algorithm and architecture co-design, this paper efficiently implements these computational and memory intensive display processing algorithms in a single chip. In particular, we describe three representative design modules in detail, including motion compensated frame rate up-conversion, content-adaptive contrast enhancement, and backlight local dimming. Extensive experiments demonstrate that the proposed design modules outperform the previous works in terms of either image quality or hardware efficiency. The overall chip is fabricated in GF 55nm CMOS technology, and can work at the maximum operating frequency of 594 MHz. The maximum input and output video formats reach up to 4K × 2K@60fps.
AB - Video display processing is an indispensable module in a variety of multimedia systems. With the increase of video format to 4K × 2K@60fps, the design of efficient display processing circuit faces severe challenges. This paper presents a video display processor which supports a variety of video formats and integrates multiple advanced algorithms for perpetual image quality improvement. By leveraging algorithm and architecture co-design, this paper efficiently implements these computational and memory intensive display processing algorithms in a single chip. In particular, we describe three representative design modules in detail, including motion compensated frame rate up-conversion, content-adaptive contrast enhancement, and backlight local dimming. Extensive experiments demonstrate that the proposed design modules outperform the previous works in terms of either image quality or hardware efficiency. The overall chip is fabricated in GF 55nm CMOS technology, and can work at the maximum operating frequency of 594 MHz. The maximum input and output video formats reach up to 4K × 2K@60fps.
KW - Video display processing
KW - backlight local dimming
KW - contrast enhancement
KW - frame rate up-conversion
KW - ultra-high definition
UR - https://www.scopus.com/pages/publications/85078847578
U2 - 10.1109/TCSI.2019.2921943
DO - 10.1109/TCSI.2019.2921943
M3 - 文章
AN - SCOPUS:85078847578
SN - 1549-8328
VL - 67
SP - 451
EP - 463
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 2
M1 - 8753508
ER -