A 14-bit 3 GS/s pipelined ADC featuring an input buffer with replica-based nonlinearity compensation in 28-nm CMOS technology

This paper presents a 3-GS/s 14-bit pipelined analog-to-digital converter (ADC) comprising an ADC core circuit, an on-chip reference circuitry, and a JESD204B serial interface for high-speed communication systems. The ADC core adopts a sample-and-hold amplifier-less (SHA-less) structure with five 3-bit pipelined stages followed by a final 4-bit flash ADC stage. In order to realize an easy-drive ADC front end with low power consumption, a source-follower-based (SFB) input buffer is integrated on chip to isolate the ADC's switch-capacitor (SC) sampling network and the external signal source. To suppress the heavy nonlinearity in the SFB input buffer, a replica-based compensation structure is proposed in which the nonlinear current flowing through the sampling capacitance is replicated to the common-mode (CM) voltage buffer for sampling via a current mirror. By simultaneously sampling both the input signal and the modulated CM voltage through the sampling capacitor, the nonlinearity is canceled significantly. The ADC with the nonlinearity-compensated input buffer is fabricated in a 28-nm CMOS process, occupying an active area of 1.46 mm². With a 2.5 V supply for the input buffer and 1 V supply for the ADC core, measurement results show that the full ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 61.08 dB and a spurious-free dynamic range (SFDR) of 75.93 dB, consuming 1.4 W of total power.