@inproceedings{9e31c96e91d8471c889845f8878c1175,
title = "A 12bit 160MS/s Pipelined SAR ADC with a MOS Self-Biased Cascoded Ring Amplifier",
abstract = "In this design, a new structure of ring amplifier (RA) is proposed to meet high-speed applications, which uses low threshold voltage transistors to increase the charge rate for capacitors. The stability is ensured by increasing the dead-zone voltage using series-connected transistors. In this design, it is utilized as an inter-stage amplifier in a 160 MS/s, 12 bits pipelined successive approximation (pipeline SAR) analog-to-digital converter (ADC). The pipeline SAR ADC is designed with a 55 nm CMOS process and occupies an overall chip area of 500 × 170 μm2. Without calibration, the dynamic performance of ADC achieves 58.56 dB for SNDR and 69.14 dB for SFDR.",
keywords = "Pipelined SAR ADC, dead-zone voltage, half-reference, ring amplifier",
author = "Qidi Li and Youze Xir and Bing Zhang and Zirui Wang and Li Geng",
note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 2023 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2023 ; Conference date: 27-10-2023 Through 29-10-2023",
year = "2023",
doi = "10.1109/ICTA60488.2023.10364249",
language = "英语",
series = "Proceedings of 2023 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2023",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "33--34",
booktitle = "Proceedings of 2023 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2023",
}