@inproceedings{48b531753e1c411b8042dfe77a44ed2c,
title = "A 100-Gb/s PAM-4 CTLE in 28-nm CMOS with Coarse-Fine Gain Adjustment",
abstract = "A 100-Gb/s continuous time linear equalizer (CTLE) for four-level pulse-amplitude modulation (PAM-4) in a 28-nm CMOS process is presented. The proposed CTLE provides peaking at Nyquist frequency, as well as peaking at mid-frequency for low-frequency channel-loss compensation. In addition, this design offers a coarse-fine tuning gain adjustment. The dc gain covers a wide range from -9dB to 12 dB with step size of less than 0.3 dB, and the peaking gain at Nyquist frequency can be adjusted from -3.4dB to 20 dB with a step size of less than 1.2 dB. The CTLE consumes 54-mW from a 0.9-V supply.",
keywords = "CTLEJ PAM-4, gain adjustment",
author = "Renjie Tang and Kanan Wang and Dan Li and Li Geng and Xiaoyan Gui",
note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 3rd IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2020 ; Conference date: 23-11-2020 Through 25-11-2020",
year = "2020",
month = nov,
day = "23",
doi = "10.1109/ICTA50426.2020.9332017",
language = "英语",
series = "Proceedings of 2020 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2020",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "92--93",
booktitle = "Proceedings of 2020 IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2020",
}