A 10-Gb/s 3.6-pA/√ Hz Input Noise Optical Receiver in 28-nm CMOS

This brief presents a 10-Gb/s optical receiver front-end that aims to replace the traditional APD with transimpedance amplifier (TIA) with a cost-effective design combining a PIN-PD and a super low-noise TIA (S-TIA). The S-TIA employed in this brief features both architecture and circuit innovation to reach the substantial noise reduction required. Additionally, an innovative on-chip integrated low-noise PD bias is proposed. According to the test results, the entire chip consumes 121 mW of power, achieves a gain of 92 dB \Omega , a bandwidth of 5.3 GHz, an input-referred noise of 259 nArms, and an input-referred noise density of 3.6 pA/√Hz. The receiver demonstrates an Optical Modulation Amplitude (OMA) sensitivity of –26.2 dBm at 10 Gb/s with a Bit Error Rate (BER) of 1E-3.