A 0.562 mm² MTJ-Based Ising Machine for 48-bit Integer Factorization in 40 nm CMOS

Combinatorial Optimization Problems (COPs) are recognized for their complexity and difficulty in finding quick solutions. An Ising machine with an annealing strategy effectively solves these COPs but often incurs low speed and high resource costs. To mitigate the challenges, we have developed a Magnetic Tunnel Junction (MTJ) technology-based CMOS Ising Machine to achieve high speed and area efficiency in solving COPs. Our main contributions include: (a) A gradient-guided strategy that shortens search times, avoiding falling into local optimal solutions; (b) A probability-based random number generator using MTJ switches to replace the high-area-cost Linear Feedback Shift Register (LFSR) circuits; (c) A digital pseudo-annealing circuit can generate interaction coefficients on-site. Fabricated with 40 nm CMOS technology, our design can achieve 48-bit (or 32-bit) integer factorization in 500 ms (or 3-5 ms) at 10-20 MHz with 1.1 V supply voltage, occupying a 0.562 mm² core area and achieving an area efficiency of up to 3846.98 mm^-2.