稳态视觉诱发电位脑机接口的现场可编程逻辑门阵列实现

To solve the problem that the steady-state visual evoked potential (SSVEP) brain-computer interface (BCI) system requires high computer performance, a SSVEP BCI system based on field programmable gate array (FPGA) and commercial electroencephalogram (EEG) acquisition device is designed by an independent display module based on FPGA. This system realizes the control of video graphics array (VGA) interface. The paradigm patterns corresponding to different flicker frequencies are allocated according to the displaying refresh frames, and the stable display of the paradigm required to induce SSVEP signals can be achieved. Collecting and analyzing the flicker outputs of the designed VGA visual stimulator, the presenting frequencies from the visual stimulator are approximately equal to the required frequencies and can be used for SSVEP BCI experiments. Combined with the designed visual stimulator, the FPGA based EEG signal processing and feature recognition are also implemented in this approach. EEG signals are transmitted to the FPGA end via the serial port, and fast Fourier transform (FFT) is used to analyze the frequency components, and these frequency components are then compared with the presenting frequencies from the visual stimulator. The overall system is verified by experiments. It is revealed that the SSVEP BCI system based on FPGA achieves an average recognition accuracy of 85.25% in the case of four stimulus targets and two seconds of single-trial time window. The proposed system can induce and recognize SSVEP signals effectively and achieve satisfactory recognition results.