VLSI implementation for video processing IP module based on synchronous and parallel architecture

Guang Lie Zhang; Nan Ning Zheng; Yong Wu; Xia Zhang

VLSI implementation for video processing IP module based on synchronous and parallel architecture

Guang Lie Zhang
, Nan Ning Zheng
, Yong Wu
, Xia Zhang

College of Artificial Intelligence and Robotics

Xi'an Jiaotong University

Research output: Contribution to journal › Article › peer-review

Abstract

This paper describes a novel design method of real time video processing, de-interlacing, color transient improvement and color space conversion, which is suitable for VLSI implementation. A synchronous and parallel pipeline architecture is proposed to reduce the complexity of video processing. The hardware design based on IP (intellectual property) module of SOC (system on a chip) is also discussed. This design is verified by Synopsys EDA tool based on 0.35 μm CMOS technology.

Original language	English
Pages (from-to)	945-948
Number of pages	4
Journal	Tien Tzu Hsueh Pao/Acta Electronica Sinica
Volume	30
Issue number	7
State	Published - Jul 2002

Keywords

IP module
Synchronous and parallel architecture
VLSI architecture
Video processing

Cite this

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title = "VLSI implementation for video processing IP module based on synchronous and parallel architecture",

abstract = "This paper describes a novel design method of real time video processing, de-interlacing, color transient improvement and color space conversion, which is suitable for VLSI implementation. A synchronous and parallel pipeline architecture is proposed to reduce the complexity of video processing. The hardware design based on IP (intellectual property) module of SOC (system on a chip) is also discussed. This design is verified by Synopsys EDA tool based on 0.35 μm CMOS technology.",

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AU - Zhang, Guang Lie

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AU - Wu, Yong

AU - Zhang, Xia

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N2 - This paper describes a novel design method of real time video processing, de-interlacing, color transient improvement and color space conversion, which is suitable for VLSI implementation. A synchronous and parallel pipeline architecture is proposed to reduce the complexity of video processing. The hardware design based on IP (intellectual property) module of SOC (system on a chip) is also discussed. This design is verified by Synopsys EDA tool based on 0.35 μm CMOS technology.

AB - This paper describes a novel design method of real time video processing, de-interlacing, color transient improvement and color space conversion, which is suitable for VLSI implementation. A synchronous and parallel pipeline architecture is proposed to reduce the complexity of video processing. The hardware design based on IP (intellectual property) module of SOC (system on a chip) is also discussed. This design is verified by Synopsys EDA tool based on 0.35 μm CMOS technology.

KW - IP module

KW - Synchronous and parallel architecture

KW - VLSI architecture

KW - Video processing

UR - https://www.scopus.com/pages/publications/0036660122

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JO - Tien Tzu Hsueh Pao/Acta Electronica Sinica

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ER -

VLSI implementation for video processing IP module based on synchronous and parallel architecture

Abstract

Keywords

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