VLSI design of the image scaling IP core with the mixed interpolation algorithm

In order to solve the problem of various input video sources displaying in flat panel display devices which have the fixed resolution without any distortion, an algorithm for image scaling based on mixed interpolation by bilinear and bicubic is proposed, and its corresponding hardware implementation is also presented. The image scaling IP core is designed by VLSI based on the mixed interpolation. The input video sources with various formats are supported by it, and the high-precision scaling function without external storage is implemented. As an embedded IP core, the image scaling core is verified to be correct in function in the digital video processing chip DTV100B. The mixed interpolation method is superior in image detail and definition preserving to bilinear interpolation, and its expense of internal memory resources is less than half that of bicubic interpolation.