VLSI design of high-speed Tier1 encoder of JPEG2000

A parallel and pipeline architecture of Tier1 encoder is proposed for JPEG2000 encoder chip. Multiple parallel and pipeline methods are adopted in a bit-plane encoder (BPE) with zero state variables' storing memory, such as dual bit-plane parallel encoding, pipeline control in pass scan, concurrent state variable's generation circuit and parallel context formation inside a column. An arithmetic encoder (AE) for multi-symbol input is implemented with parallel and pipeline architecture; synchronous accessing circuit for input-symbols is also designed for variable arithmetic encoding cycles; they make coding pairs of CX/D up to 1.3 pair/cycle on average. Memory storing for compressed code from arithmetic encoder is efficiently implemented as macro pipeline. The Tier1 encoder's maximum rate is up to 85 M wavelet coefficients per-second at 100 MHz. Synthesized with SMTC 0.25 μm library in Synopsys DC, the equivalent gates of NAND2 are about 63 K, there is 26 Kb on-chip memory (code block size 32 × 32) and the critical path is 5.2 ns.