TY - GEN
T1 - VLSI design of fuzzy-decision bit-flipping QC-LDPC decoder
AU - Zhao, Wenzhe
AU - Lv, Minjie
AU - Sun, Hongbin
AU - Zheng, Nanning
AU - Zhang, Tong
PY - 2013
Y1 - 2013
N2 - In MLC NAND flash system, the hybrid hard-decision /soft-decision LDPC decoder prefers a high throughput bit-flipping decoder. Therefore, the high-efficiency silicon implementation of bit-flipping decoder becomes a practically relevant topic. This paper presents a so-called fuzzy-decision bit-flipping decoding algorithm to reduce the hardware consumption and average iteration numbers. Simulations and VLSI design show that the proposed design solution can improve upto 10% higher decoding throughput, and meanwhile reduce upto 40% less silicon cost, without performance reducing.
AB - In MLC NAND flash system, the hybrid hard-decision /soft-decision LDPC decoder prefers a high throughput bit-flipping decoder. Therefore, the high-efficiency silicon implementation of bit-flipping decoder becomes a practically relevant topic. This paper presents a so-called fuzzy-decision bit-flipping decoding algorithm to reduce the hardware consumption and average iteration numbers. Simulations and VLSI design show that the proposed design solution can improve upto 10% higher decoding throughput, and meanwhile reduce upto 40% less silicon cost, without performance reducing.
UR - https://www.scopus.com/pages/publications/84901299075
U2 - 10.1109/ASICON.2013.6811972
DO - 10.1109/ASICON.2013.6811972
M3 - 会议稿件
AN - SCOPUS:84901299075
SN - 9781467364157
T3 - Proceedings of International Conference on ASIC
BT - 2013 IEEE 10th International Conference on ASIC, ASICON 2013
PB - IEEE Computer Society
T2 - 2013 IEEE 10th International Conference on ASIC, ASICON 2013
Y2 - 28 October 2013 through 31 October 2013
ER -