VLSI design of edge-preserving coding artifacts reduction for display processing

Although coding artifacts reduction is one of indispensable modules in video display processing system, its VLSI design is still rarely studied. Existing coding artifacts reduction approaches mainly focus on in-loop techniques, the other post-processing methods have not addressed the challenges posed by display system and are actually inapplicable to real-time display processing. This paper proposes an efficient algorithm which can reduce both blocking and ringing artifacts while effectively preserving edge and texture regions. The proposed algorithm is inherently hardware-friendly, and is implemented with a fully pipelined VLSI architecture which is synchronized to pixel clock and can be easily integrated into display processing system. Evaluation results demonstrate that, the image quality of the proposed algorithm outperforms four previously proposed post-processing approaches, and its VLSI circuit can achieve the real-time performance of 1080P@60Hz at the cost of less than 63K logic gates and 15.4KB memories.