Transient circuit simulation model of saturable reactors for HVDC converter valves

In order to analysis the turn-on and turn-off stress of a high voltage direct current (HVDC) converter valve, the transient circuit simulation model of saturable reactors was built. The simulation model of a saturable reactor was regarded as a no-load transformer, whose magnetizing inductance and leakage inductance correspond to the magnetic-core and air-core inductance of saturable reactors respectively. The nonlinear inductance of magnetic cores used was equivalent to a current source controlled by its linked volts-sec in order to reduce the calculation errors caused by differentials. The eddy-current resistance is calculated using the improved wave penetration theory. By doing so, the accuracy and convergence properties of simulation model proposed were greatly improved. The capacitor discharging experiments were conducted to verify the parameters of saturable reactors. It can be seen that the simulation waveforms had a good agreement with those abstained from high voltage (HV) discharging experiments.