Theoretical Model of EⁿDP to Achieve Energy-Efficient SRAM

New tradeoff metric of the energyⁿ-delay product (EⁿDP, n>1) for energy efficiency design is proposed in this paper. Compared with the conventional energy-delay product metric, the new metric puts more weight on energy than delay, more suitable for those power-critical mid/low-speed applications. We first establish the theoretical model, and then provide comprehensive optimum design points for various processes and applications as energy-efficient design guidelines. We also find that the optimum EⁿDP operation coincides with the well-known near-threshold methodology, and discuss the challenges and possible design methods. An enhanced hierarchical bit-line structure along with 8T-SRAM cell and local read/write assist circuits is introduced for robust operation and energy efficiency improvement, facilitating EⁿDP methodology. Finally, an 8-kb SRAM macro in 180-nm CMOS technology for ultra-low-power applications is designed and fabricated to validate the methodology, where a supply voltage of 1.54 is applied to obtain maximum energy efficiency based on E²DP metric. The minimum E²DP of 610 pJ²/GHz is obtained at 0.65 V, fitting the theoretical analysis accurately. Power consumption at 0.65 V is , only 2.6% of that at nominal voltage, 1.8 V. The test chip can operate correctly from 1.8to 0.6 V with frequency scaling from 400 to 15.5 MHz.