Abstract
The exponential growth of AI-driven High-Performance Computing (HPC) has catalyzed a transition toward 2.5D heterogeneous integration, engendering a congested thermal landscape characterized by extreme power densities and complex inter-chip thermal crosstalk. To address these challenges, this study reports a parallel embedded manifold microchannel cooling (pEMMC) architecture specifically engineered for 2.5D heterogeneous packages. Unlike conventional remote cooling or sparse chip array solutions, we developed a high-fidelity, silicon-based 2.5D thermal test vehicle (TTV) that incorporates industry-standard packaging features, including organic epoxy molding compound (EMC) and high-density redistribution layers (RDL). Experimental results demonstrate that the pEMMC architecture enables each individual chiplet to approach its intrinsic cooling limit, with unit-area thermal resistances minimized to 0.134–0.159 cm2·K/W. At the system level, the prototype successfully dissipated a highly competitive aggregate power of 948 W with an exceptionally low thermal resistance of 0.083 K/W, maintaining junction temperature rises below 80 K at heat fluxes up to 400 W/cm2. Furthermore, a transient thermal RC network was established to evaluate the spatiotemporal thermal dynamics and provide a conceptual framework for understanding the highly effective crosstalk suppression. The analysis elucidates how the parallel hydraulic topology ensures thermal decoupling between chiplets, substantially mitigating crosstalk under heterogeneous workloads. These advances offer a scalable methodology for managing the thermal frontiers of future chiplet-based systems and AI infrastructure.
| Original language | English |
|---|---|
| Article number | 131418 |
| Journal | Applied Thermal Engineering |
| Volume | 300 |
| DOIs | |
| State | Published - Jul 2026 |
| Externally published | Yes |
Keywords
- Chiplet
- Embedded cooling
- Heterogeneous integration
- Manifold microchannel
- Thermal crosstalk
- Thermal management
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