TY - GEN
T1 - Suppression on Crosstalk Voltages of Paralleled SiC MOSFETs with Optimized Gate Configurations and Additional SiC SBDs
AU - Zhao, Cheng
AU - Wang, Laili
AU - Yang, Juhui
AU - Wu, Shijie
AU - Gan, Yongmei
AU - Cui, Hongchang
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - It is popular to parallel SiC MOSFETs for high-current applications. Compared with the single SiC MOSFET chip, the cross-turn-ON issues of paralleled SiC MOSFETs (PSMs) will be more complicated because of various mismatches in PSMs. This paper investigates the effects of all possible mismatches on the spurious gate-source voltages of PSMs (crosstalk voltages) by theoretical analysis and experiments. It is found that mismatched body diodes, asymmetric power-net layout and uneven junction temperature for PSMs can increase crosstalk voltages, leading to higher cross-turn-ON risk. Then the proportion of overall and separate gate resistance is adjusted and additional SiC Schottky Barrier diodes (SBDs) are employed to suppress crosstalk voltages of PSMs due to these mismatches. The effectiveness of both methods has be verified by experiments.
AB - It is popular to parallel SiC MOSFETs for high-current applications. Compared with the single SiC MOSFET chip, the cross-turn-ON issues of paralleled SiC MOSFETs (PSMs) will be more complicated because of various mismatches in PSMs. This paper investigates the effects of all possible mismatches on the spurious gate-source voltages of PSMs (crosstalk voltages) by theoretical analysis and experiments. It is found that mismatched body diodes, asymmetric power-net layout and uneven junction temperature for PSMs can increase crosstalk voltages, leading to higher cross-turn-ON risk. Then the proportion of overall and separate gate resistance is adjusted and additional SiC Schottky Barrier diodes (SBDs) are employed to suppress crosstalk voltages of PSMs due to these mismatches. The effectiveness of both methods has be verified by experiments.
KW - Body diode mismatches
KW - Crosstalk voltages
KW - Junction temperature differences
KW - Layout Asymmetries
KW - Paralleled SiC MOSFETs
UR - https://www.scopus.com/pages/publications/85170374416
U2 - 10.1109/PEDG56097.2023.10215177
DO - 10.1109/PEDG56097.2023.10215177
M3 - 会议稿件
AN - SCOPUS:85170374416
T3 - PEDG 2023 - 2023 IEEE 14th International Symposium on Power Electronics for Distributed Generation Systems
SP - 1067
EP - 1071
BT - PEDG 2023 - 2023 IEEE 14th International Symposium on Power Electronics for Distributed Generation Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 14th IEEE International Symposium on Power Electronics for Distributed Generation Systems, PEDG 2023
Y2 - 9 June 2023 through 12 June 2023
ER -
