Stacked Multi-Channel Receiver Architecture for Power-Efficient High-Speed Optical Links

The power supply discrepancy between advanced CMOS technology and legacy optical module leads to poor power efficiency or extra DC-DC component. A new stacked multi-channel receiver architecture and its synergetic power supply scheme for power-efficient optical links are proposed to solve the problem. Consequently, power reduction can be achieved thanks to the full utilization of available power supply headroom and the reuse of supply current. As a proof of concept, a stacked 2 × 10 Gb/s optical receiver with a synergetic-integrated linear multi-output regulator is implemented in 0.18- μ m CMOS technology, demonstrating the feasibility of the proposed architecture. State-of-the-art receiver performance and power efficiency are achieved.