TY - GEN
T1 - Simplified Space Vector Modulation Strategy for Three-level Inverters
AU - Woldegiorgis, Dereje
AU - Soria, Estefano
AU - Wei, Yuqi
AU - Mhiesan, Haider
AU - Mantooth, Alan
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/3
Y1 - 2020/3
N2 - This paper presents a simplified space vector modulation strategy for three-level inverter digital control applications. It avoids the complex trigonometric computations necessary for the conventional three-level space vector modulation strategy for sector identification and vector dwell time calculation by directly determining the phase duty ratios from the three-phase reference voltages. This implementation technique only involves few logic comparisons and arithmetic operations, so the code size and execution time are reduced by approximately 40 percent. Moreover, it achieves significantly lower neutral-point voltage ripple compared to the conventional three-level space vector modulation method for a wide range of modulation indices and load power factor values. The validity of the proposed modulation technique is verified using Opal-RT Hardware-in-the-Loop (HIL) simulation. The simulation results confirm that the proposed method ensures the required threelevel operation and dc-link capacitor voltage balancing.
AB - This paper presents a simplified space vector modulation strategy for three-level inverter digital control applications. It avoids the complex trigonometric computations necessary for the conventional three-level space vector modulation strategy for sector identification and vector dwell time calculation by directly determining the phase duty ratios from the three-phase reference voltages. This implementation technique only involves few logic comparisons and arithmetic operations, so the code size and execution time are reduced by approximately 40 percent. Moreover, it achieves significantly lower neutral-point voltage ripple compared to the conventional three-level space vector modulation method for a wide range of modulation indices and load power factor values. The validity of the proposed modulation technique is verified using Opal-RT Hardware-in-the-Loop (HIL) simulation. The simulation results confirm that the proposed method ensures the required threelevel operation and dc-link capacitor voltage balancing.
KW - Capacitor voltage Balance
KW - Digital Control
KW - Neutral-point voltage ripple
KW - Space Vector Modulation
KW - Three-level inverter
UR - https://www.scopus.com/pages/publications/85087758726
U2 - 10.1109/APEC39645.2020.9124284
DO - 10.1109/APEC39645.2020.9124284
M3 - 会议稿件
AN - SCOPUS:85087758726
T3 - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 2963
EP - 2967
BT - APEC 2020 - 35th Annual IEEE Applied Power Electronics Conference and Exposition
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 35th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2020
Y2 - 15 March 2020 through 19 March 2020
ER -