TY - GEN
T1 - Simple carrier based capacitor voltage balancing technique for three-level voltage source inverters
AU - Woldegiorgis, Dereje
AU - Wei, Yuqi
AU - Mantooth, Alan
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021/6/14
Y1 - 2021/6/14
N2 - This paper presents a simple carrier-based dc-link capacitor voltage balancing technique for three-level voltage source inverters. It modifies the amplitudes of the two carrier signals based on the dc-link capacitor voltage deviations to regulate the charging and discharging of the dc-link capacitors. This capacitor voltage balancing method is simple and suitable for implementation in low power microcontrollers. Compared to the conventional dc-link capacitor voltage balancing method based on Space Vector Modulation (SVM) strategy, the proposed voltage balancing method reduces both code size and execution time by 40 percent. In addition, it provides tight neutral-point potential regulations for a wide range of modulation indices and load power factor values. The only drawback of the proposed voltage balancing method is its slightly higher switching loss and output current ripple compared to the conventional SVM based dc-link capacitor voltage balancing method. The validity of the proposed dc-link voltage balancing method is verified using experimental test.
AB - This paper presents a simple carrier-based dc-link capacitor voltage balancing technique for three-level voltage source inverters. It modifies the amplitudes of the two carrier signals based on the dc-link capacitor voltage deviations to regulate the charging and discharging of the dc-link capacitors. This capacitor voltage balancing method is simple and suitable for implementation in low power microcontrollers. Compared to the conventional dc-link capacitor voltage balancing method based on Space Vector Modulation (SVM) strategy, the proposed voltage balancing method reduces both code size and execution time by 40 percent. In addition, it provides tight neutral-point potential regulations for a wide range of modulation indices and load power factor values. The only drawback of the proposed voltage balancing method is its slightly higher switching loss and output current ripple compared to the conventional SVM based dc-link capacitor voltage balancing method. The validity of the proposed dc-link voltage balancing method is verified using experimental test.
KW - Capacitor voltage Balance
KW - Digital Control
KW - Neutral-point voltage ripple
KW - Three-level inverter
UR - https://www.scopus.com/pages/publications/85115711537
U2 - 10.1109/APEC42165.2021.9487338
DO - 10.1109/APEC42165.2021.9487338
M3 - 会议稿件
AN - SCOPUS:85115711537
T3 - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 528
EP - 533
BT - 2021 IEEE Applied Power Electronics Conference and Exposition, APEC 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 36th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2021
Y2 - 14 June 2021 through 17 June 2021
ER -