POSTER: Bring I-Cache to Light in Data Plane Applications

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Modern data plane applications are usually with large code, causing the i-cache to miss frequently during execution. To this end, we apply a new execution model on these applications that splits them into i-cache-friendly stages, and reuse the code of each stage on multiple packets. Experiments on snort3 show that i-cache misses are reduced by 72.2%, and throughput increases by 25.0%.

Original languageEnglish
Title of host publicationSIGCOMM Posters and Demos 2024 - Proceedings of the 2024 SIGCOMM Poster and Demo Sessions, Part of
Subtitle of host publicationSIGCOMM 2024
PublisherAssociation for Computing Machinery, Inc
Pages28-30
Number of pages3
ISBN (Electronic)9798400707179
DOIs
StatePublished - 5 Aug 2024
Event2024 SIGCOMM Poster and Demo Sessions, SIGCOMM Posters and Demos 2024, part of SIGCOMM 2024 - Sydney, Australia
Duration: 4 Aug 20248 Aug 2024

Publication series

NameSIGCOMM Posters and Demos 2024 - Proceedings of the 2024 SIGCOMM Poster and Demo Sessions, Part of SIGCOMM 2024

Conference

Conference2024 SIGCOMM Poster and Demo Sessions, SIGCOMM Posters and Demos 2024, part of SIGCOMM 2024
Country/TerritoryAustralia
CitySydney
Period4/08/248/08/24

Keywords

  • data plane
  • instruction cache

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